1. Field of the Invention
This invention relates to logic and memory devices in which a memory system for storing data is constructed on a common semiconductor substrate with a logic circuit that accesses data stored by the memory system.
2. Description of Related Art
There are numerous applications in which a digital logic circuit needs to use data stored in a memory system. In the majority of these applications, the memory system is constructed on a separate memory chip designed with a standardized set of inputs and outputs through which the data must be accessed. These standardized inputs and outputs allow the memory chip to be used for different applications, but they limit the communication between the memory system and the logic circuit.
A logic circuit for performing a particular digital function is commonly referred to as a "macro". In order to reduce cost, newer digital designs may have the memory system constructed on a common substrate with the logic circuit, and such a device is referred to herein as an embedded memory macro. Individual macros may be combined and constructed on a single substrate to create a more complex digital circuit. Alternatively, the individual macros may be constructed as separate devices.
Although embedded memory macro designs are known, they have heretofore used the same standardized set of inputs and outputs for communication between the embedded memory system and the associated logic circuitry. That standardized interface prevents the memory system from signaling to the logic circuit when data that has been read from the memory has become valid, even though newer memory system designs have this information internally available to the memory system.
Accordingly, one object of the present invention is to improve embedded memory macro performance by communicating additional information between the memory system and the logic circuit. This object is achieved by taking advantage of the fact that an embedded memory system is constructed on the same substrate as the logic circuitry, allowing the interface between the two to be improved and to carry more information.
In a conventional macro, where the memory and logic are on separate chips, the memory will have been tested after construction and certified to meet certain specifications. The macro can be designed with these memory specifications in mind and the memory and the macro can be matched. In an embedded memory macro, however, this matching cannot be done. The embedded memory macro needs to be designed with the possibility that there will be variations in the memory system performance. This has required either very conservative design, resulting in less than optimum performance for the macro, or complex initialization and testing of the memory by the macro at startup to adjust macro operation to the memory system performance.
Accordingly, another object of the invention is to avoid the necessity for complex initialization and testing of the memory system by the macro to compensate for variations in memory system performance. This object can also be achieved through improving the interface and communication between the memory system and the logic circuit.
The present invention contemplates the use of a newer type of memory system which uses internal signals, usually referred to as "interlock signals" or "dummy data line" signals, for controlling the flow of data in the memory system. U.S. Pat. No. 5,383,155 issued to Ta on Jan. 17, 1995, is illustrative of one application of an interlocked design.
The interlock signals, which have heretofore been used only for read operations and which have only been used internally within the memory system, are used in the present invention to construct a system interlock signal that tells the logic circuitry when the memory system has successfully completed a read operation. The design of the logic circuit is adjusted to allow this information to be used to optimize performance of the embedded memory macro.
Yet another object of the invention relates to improving performance of the embedded memory macro during the write operation. The design of the memory system is adjusted to monitor the write operation as well as the read operations and to produce an interlock signal indicating when a write operation has been successfully completed. This allows the memory system to provide information concerning the write operation to the logic circuit, allowing the logic circuit to adjust its write and read cycles accordingly.
Because it is relatively easy to design the write operation of a memory system to be at least as fast as the read operation, memory systems have not previously been designed to use interlock signals during the write operation in the way that they have been used during the read operation. Further, there has been little incentive to improve the write operation speed beyond the speed of the read operation when both operations are designed simply to be completed within a defined access time.
In the preferred design of the present invention the logic circuit uses the information provided by the memory system about the successful completion of each individual read/write operation to speed up or slow down the subsequent memory operation. This allows the entire macro to constantly run at the optimum speed. This results in a system that is far superior to a non-embedded memory macro design, even where the separate memory system has been carefully matched to the logic circuit.
Specifically, the embedded memory macro of this invention self-adjusts and varies its performance for each individual read or write operation to optimally match the performance of the memory system. The matching occurs regardless of whether the variation of the memory system is the result of manufacturing process variations, ambient operating environment variations, or task speed variations depending upon where in the array of memory cells in the memory system the data is being stored.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.